1. Field of the Invention
This invention relates generally to digital devices, and more particularly, to a digital device having an internal differential signal generator.
2. Description of the Related Art
The operating speeds of digital devices continues to increase, driven by expectations of continual performance gain. One technique for increasing the performance of a digital device involves the use of differential signaling to send and receive data at higher speeds. Digital devices, such as memory devices, often use differential signaling to generate differential clock signals for use by the device.
A differential clock signal is generated by passing an external clock signal (CLK) and an external inverted clock signal ({overscore (CLK)}) to a differential receiver. The differential receiver outputs a logic high level when the CLK signal is greater than the {overscore (CLK)} signal and a logic low level when the CLK signal is lesser an the {overscore (CLK)} signal. The fact that both the CLK signal and the {overscore (CLK)} signal are transitioning at the same time provides a cleaner transition for generating the differential clock signal.
FIG. 4 is a timing diagram illustrating the relationship between the CLK signal, the {overscore (CLK)} signal, and an exemplary output clock signal of the digital receiver, DCLK. The DCLK signal may be a single signal (as shown) or a differential signal having complimentary components.
Typically, digital devices are tested by a low speed testing system to determine their proper function. A single test unit may test a large number of devices simultaneously. During the test, the test unit supplies the logic signals required to operate the device. Devices that use differential signaling have external pins for receiving the CLK signal and the {overscore (CLK)} signal. Many low speed test systems have limited pin resources, yet the devices being tested have increasing pin counts due to the use of differential signaling. As a result, it becomes more difficult to supply the number of logic signals required to test a large number of devices in parallel.
One technique for reducing the pin resource demand on the test unit is to couple one of the differential signal input pins on the device to a reference voltage (e.g. half of the operating voltage, Vcc). Thus, the differential receiver transitions when the other signal of the differential pair passes through the reference voltage. In this configuration, the test unit is only required to provide one half of the differential pair, thus reducing the pin resource demands on the test unit.
The technique of tying one of the differential inputs to a reference voltage has at least one shortcoming in that high speed differential receivers work best when both of the inputs are changing concurrently. When only one signal of the differential pair is changing, the stability and effectiveness of the differential receivers are reduced. This deleteriously affects the ability of the test unit to test multiple devices in parallel.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a device including a first input pin, a second input pin, a differential signal generator, and a differential receiver. The first input pin is adapted to receive a first signal. The second input pin is adapted to receive a second signal. The differential signal generator is coupled to the first and second input pins and adapted to receive an enable signal. The differential signal generator is adapted to isolate the second input pin and generate an internal signal based on an inversion of the first signal in response to the enable signal being asserted. The differential receiver has a first input terminal and a second input terminal. The differential receiver is adapted to receive the first signal at the first input terminal and one of the second signal and the internal signal at the second input terminal and generate a differential output signal.
Another aspect of the present invention is seen in a method for generating a differential signal. A first input signal is received at a first input pin of a device. An enable signal is received. A second input pin of the device is isolated based on the enable signal. An internal signal is generated based on an inversion of the first signal. The differential signal is generated based on the first signal and the internal signal.